Instruction and logic for a cache prefetcher and dataless fill buffer
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United States of America Patent
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Jan 31, 2017
Grant Date -
Mar 10, 2016
app pub date -
Sep 9, 2014
filing date -
Sep 9, 2014
priority date (Note) -
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Abstract
A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.
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