Processing system with synchronization instruction
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United States of America Patent
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-
Jan 31, 2017
Grant Date -
Jul 7, 2016
app pub date -
Mar 17, 2016
filing date -
Dec 6, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.
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