Timing violation handling in a synchronous interface memory

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United States of America Patent

PATENT NO 9558799
APP PUB NO 20160086662A1
SERIAL NO

14954587

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Abstract

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A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ferrario, Marco Milan, IT 10 88
Laurent, Christophe Vincent Antoine Agrate Brianza, IT 42 119
Mastroianni, Francesco Melzo, IT 11 21

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