Memory cell that prevents charge loss
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United States of America Patent
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Jan 31, 2017
Grant Date -
May 7, 2015
app pub date -
Oct 31, 2012
filing date -
Oct 31, 2012
priority date (Note) -
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Abstract
A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.
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