Optimized structure for hexadecimal and binary multiplier array
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United States of America Patent
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Feb 7, 2017
Grant Date -
Mar 24, 2016
app pub date -
Sep 18, 2014
filing date -
Sep 18, 2014
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Abstract
A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.
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Patent Owner(s)
- INTERNATIONAL BUSINESS MACHINES CORPORATION
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Dao, Trong Son | Stuttgart, DE | 7 | 151 |
Mueller, Silvia M | Altdorf, DE | 75 | 253 |
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