Techniques for cooperative execution between asymmetric processor cores
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United States of America Patent
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Feb 7, 2017
Grant Date -
Jun 30, 2016
app pub date -
Dec 26, 2014
filing date -
Dec 26, 2014
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Abstract
Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
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