Non-volatile memory device and corresponding operating method with stress reduction
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United States of America Patent
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Feb 7, 2017
Grant Date -
Dec 1, 2016
app pub date -
Dec 16, 2015
filing date -
May 27, 2015
priority date (Note) -
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Abstract
A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.
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