Instruction and logic for accelerated compressed data decoding
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United States of America Patent
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Feb 7, 2017
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N/A
app pub date -
Dec 18, 2015
filing date -
Dec 18, 2015
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Abstract
A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value generator, and a decoder. The code information array includes a pre-computed code length counter and a pre-computed last code. The matching logic unit includes logic using the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index. The code value generator includes logic to translate the matching code index into a code value. The decoder includes logic to generate decompressed data from the code value and the matching code length.
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