Delay fault testing for chip I/O

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9568546
APP PUB NO 20130314102A1
SERIAL NO

13982471

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Franzon, Paul D New Hill, US 20 254

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