Memory system controlling interleaving write to memory chips

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United States of America Patent

PATENT NO 9569117
SERIAL NO

14447810

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Abstract

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According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kojima, Yoshihisa Kawasaki, JP 152 1112
Ueki, Katsuhiko Katsushika, JP 38 421

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