Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm

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United States of America Patent

PATENT NO 9569210
APP PUB NO 20160313993A1
SERIAL NO

15203610

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Abstract

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An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dixon, Martin G Portland, US 135 1467
Feghali, Wajdi K Boston, US 156 1450
Gopal, Vinodh Westborough, US 365 2582
Guilford, James D Northborough, US 152 1286
Gulley, Sean M Boston, US 48 499
Ozturk, Erdinc Hillsboro, US 77 661
Wolrich, Gilbert M Framingham, US 177 1941
Yap, Kirk S Westborough, US 109 925

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