Instruction and logic for a memory ordering buffer
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United States of America Patent
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Feb 14, 2017
Grant Date -
Oct 1, 2015
app pub date -
Mar 28, 2014
filing date -
Mar 28, 2014
priority date (Note) -
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Abstract
A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests.
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