Reduced-overhead error detection and correction

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United States of America Patent

PATENT NO 9569308
SERIAL NO

14328941

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Abstract

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A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Leibowitz, Brian S San Francisco, US 129 1619
Ware, Frederick A Los Altos Hills, US 758 10954

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