Managing error data and resetting a computing system
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United States of America Patent
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Feb 14, 2017
Grant Date -
Apr 2, 2015
app pub date -
Oct 1, 2013
filing date -
Oct 1, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
Various techniques for managing a system reset of a computing system to maintain error data are described herein. In one example, a computing system configured for managing a system reset to maintain error data comprises a memory buffer device to receive a transaction from a system processor and to notify the system processor of an error in performing the transaction to volatile memory. In some examples, the system processor is configured to initiate a system reset of the computing system in response to the error, the system reset comprising a reset of the memory buffer device. Furthermore, the computing system includes an integrated circuit to block the reset of the memory buffer device to maintain error data in the volatile memory.
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