Methods and apparatuses for addressing memory caches

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United States of America Patent

PATENT NO 9569359
SERIAL NO

14001464

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Abstract

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A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Diep, Trung San Jose, US 13 160
Zheng, Hongzhong Sunnyvale, US 239 1085

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