System and method for performing memory operations on RRAM cells
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United States of America Patent
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Feb 14, 2017
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N/A
app pub date -
Aug 10, 2012
filing date -
Aug 24, 2011
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Abstract
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
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