1D-2R memory architecture

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United States of America Patent

PATENT NO 9570165
SERIAL NO

14568011

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Abstract

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A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.

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Patent Owner(s)

  • RAMBUS INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bronner, Gary Bela Los Altos, US 39 401
Chevallier, Christophe J Palo Alto, US 246 7966
Ertosun, Mehmet Gunhan Mountain View, US 2 12
Friend, Elizabeth Sunnyvale, US 3 25
Sekar, Deepak Chandra San Jose, US 57 988
Swab, Philip F S Santa Rosa, US 11 135
Vereen, Lidia San Ramon, US 10 111

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