Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same
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United States of America Patent
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Feb 14, 2017
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N/A
app pub date -
Mar 24, 2016
filing date -
Mar 24, 2016
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Abstract
The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device.
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