Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping
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United States of America Patent
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Feb 21, 2017
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N/A
app pub date -
Feb 10, 2016
filing date -
Oct 14, 2015
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Abstract
A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.
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