Mixed-width memory techniques for programmable logic devices
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United States of America Patent
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Feb 21, 2017
Grant Date -
Dec 31, 2015
app pub date -
Jun 30, 2014
filing date -
Jun 30, 2014
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Abstract
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.
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