Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
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United States of America Patent
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Feb 21, 2017
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app pub date -
Oct 22, 2015
filing date -
Jul 6, 2012
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Abstract
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
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