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Abstract

A decision feedback equalizer (DFE) includes first through sixth flip-flops, and first and second summer circuits. The first through fourth flip-flops sample an analog input signal received at the first and second summer circuits, detect the logic level of a data bit in the analog input signal and generate the first through fourth compensated signals. The first multiplexer outputs at least one of the first and second compensated signals as a first feedback signal, based on a fourth feedback signal generated by the sixth flip-flop. The second multiplexer outputs at least one of the third and fourth compensated signals as a second feedback signal, based on a third feedback signal generated by the fifth flip-flop. The first and second feedback signals are multiplied by a weight coefficient and fed back to the first and second summer circuit, respectively, to compensate an error in the analog input signal.

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First Claim