Method and system for template pattern optimization for DSA patterning using graphoepitaxy
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United States of America Patent
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Feb 28, 2017
Grant Date -
Dec 1, 2016
app pub date -
Jun 25, 2015
filing date -
May 28, 2015
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Abstract
A method for design template pattern optimization, comprises receiving a design for a fin field effect transistor (FinFET) device, wherein the design includes a configuration of fins, creating a design template pattern for the design for use in connection with directed self-assembly (DSA) patterning using graphoepitaxy, and optimizing the design template pattern to minimize pattern density gradients, wherein the design template pattern includes a plurality of guiding lines for guiding a block-copolymer deposited during the DSA patterning and the optimizing comprises altering the guiding lines.
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