Receiver equalization circuit with cross coupled transistors and/or RC impedance
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United States of America Patent
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Feb 28, 2017
Grant Date -
N/A
app pub date -
Dec 2, 2015
filing date -
Dec 2, 2015
priority date (Note) -
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Abstract
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and (b) a combined resistive and capacitive load between the first and second differential write lines. The second circuit may be configured to (a) convert the first and the second differential write signals to a single-ended write signal and (b) present the single-ended write signal to the data bus.
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