Gate structure integration scheme for fin field effect transistors
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United States of America Patent
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Feb 28, 2017
Grant Date -
Apr 28, 2016
app pub date -
Dec 31, 2015
filing date -
Feb 7, 2014
priority date (Note) -
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Abstract
In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.
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