Multiple FET non-volatile memory with default logical state

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United States of America Patent

PATENT NO 9589639
SERIAL NO

14932142

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Abstract

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A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The first set of FETs has a first channel width. A second set of FETs of the plurality of FETs is coupled to a bitline complement of the memory array. The second set of FETs has a second channel width. The first channel width is greater than the second channel width. The channel width disparity provides the NVM element of the unprogrammed memory array with a default state.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Erickson, Karl R Rochester, US 73 487
Kilker, Robert E Rochester, US 6 8
Paone, Phil C Rochester, US 79 502
Paulsen, David P Inver Grove Heights, US 98 600
Sheets,, II John E Zumbrota, US 133 570
Uhlmann, Gregory J Rochester, US 76 469

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