Method for integrated circuit patterning

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United States of America Patent

PATENT NO 9589800
APP PUB NO 20160071730A1
SERIAL NO

14846112

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Abstract

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A method of forming a target pattern includes forming a plurality of lines over a substrate and forming spacer features on sidewalls of the lines. The method further includes shrinking the spacer features using a wet process. After the shrinking of the spacer features, the method further includes removing the lines thereby providing the shrunk spacer features over the substrate.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDNO 8 LI-HSIN RD VI HSINCHU SCIENCE PARK HSINCHU 300

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsieh, Ching-Hua Hsinchu, TW 265 2259
Huang, Huang-Yi Hsin-Chu, TW 48 240
Tung, Szu-Ping Taipei, TW 42 254
Yang, Neng-Jye Hsinchu, TW 48 63

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