Package structure and manufacturing method thereof
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United States of America Patent
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Mar 7, 2017
Grant Date -
Jun 9, 2016
app pub date -
Mar 31, 2015
filing date -
Dec 8, 2014
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate includes a first patterned metal layer, a second patterned metal layer, a first surface and a second surface. The first and second patterned metal layers are disposed on the first and second surfaces. The patterned solder mask disposed on the first and second patterned metal layers exposes part of the first and second patterned metal layers. The first thermal-conductive posts are disposed on the exposed first patterned metal layer and thermally coupled thereto. The chip is disposed on the first surface. The chip electrically connected to the first patterned metal layer is thermally coupled to the first thermal-conductive posts. Two opposite ends of each first thermal-conductive post are connected to the first and second substrates, and the first thermal-conductive posts are thermally coupled to the second substrate.
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