III-V gate-all-around field effect transistor using aspect ratio trapping
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United States of America Patent
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Mar 7, 2017
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app pub date -
Jun 25, 2015
filing date -
Jun 25, 2015
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Abstract
Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate. A channel feature comprising III-V material is subsequently formed inside the trench. Source/drain features are then formed at both ends of the channel feature inside the trench. Lastly, gate dielectric layers and a gate feature are formed surrounding a portion of the channel feature.
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