Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers

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United States of America Patent

PATENT NO 9590167
APP PUB NO 20160359099A1
SERIAL NO

15248488

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Abstract

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A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Elmegreen, Bruce G Golden's Bridge, US 34 902
Martyna, Glenn J Croton on Hudson, US 51 560
Newns, Dennis M Yorktown Heights, US 81 1444

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