Interface between a bus and a inter-thread interconnect
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United States of America Patent
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Mar 14, 2017
Grant Date -
Apr 23, 2015
app pub date -
Oct 21, 2013
filing date -
Oct 21, 2013
priority date (Note) -
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Abstract
A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.
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