Programmable device using fixed and configurable logic to implement recursive trees
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United States of America Patent
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Mar 21, 2017
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N/A
app pub date -
Jul 15, 2013
filing date -
May 9, 2011
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Abstract
A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a direct-connect input for connection to a first other instance of the specialized processing block, and a direct-connect output for connection to a second other instance of the specialized processing block. A plurality of instances of the specialized processing block are together configurable as a binary or ternary recursive adder tree.
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