Absolute address branching in a fixed-width reduced instruction set computing architecture
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United States of America Patent
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Mar 28, 2017
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N/A
app pub date -
Sep 5, 2014
filing date -
May 30, 2014
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Abstract
Embodiments relate to a method and computer program product for absolute address branching in a reduced instruction set computing (RISC) architecture. One aspect is a method that includes fetching a branch instruction from an instruction stream having a fixed instruction width. A branch target address value is acquired from the instruction stream. The branch target address value represents a target address of the branch instruction. The branch target address value is formatted as an absolute address and sized as a multiple of the fixed instruction width. The branch target address value is loaded into a program counter based on the branch instruction. Execution of the instruction stream is redirected to a next instruction based on the branch target address value in the program counter.
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