Apparatus and method for drift cancellation in a memory
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United States of America Patent
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Apr 4, 2017
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app pub date -
Mar 27, 2015
filing date -
Mar 27, 2015
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Abstract
An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
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