Collapsing of multiple nested loops, methods and instructions
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United States of America Patent
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Apr 11, 2017
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app pub date -
Dec 27, 2012
filing date -
Dec 27, 2012
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Abstract
In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.
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