Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

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United States of America Patent

PATENT NO 9619356
APP PUB NO 20160092331A1
SERIAL NO

14963296

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Abstract

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A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cain,, III Harold W Katonah, US 92 1349
Daly, David M Croton-on-Hudson, US 40 522
Ekanadham, Kattamuri Mohegan Lake, US 56 1062
Huang, Michael C Rochester, US 12 173
Moreira, Jose E Irvington, US 72 736
Serrano, Mauricio J Bronx, US 43 712

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