Scalable geometry processing within a checkerboard multi-GPU configuration

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United States of America Patent

PATENT NO 9619855
APP PUB NO 20140306949A1
SERIAL NO

13976843

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Abstract

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Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boles, Jeffery S Folsom, US 60 231
Doyle, Peter L El Dorado Hills, US 68 672
Hunter, Jr Arthur D Camerson Park, US 3 16
Koker, Altug El Dorado Hills, US 517 2113
Navale, Aditya Folsom, US 93 938

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