Stacked-die memory systems and methods for training stacked-die memory systems
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United States of America Patent
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Apr 11, 2017
Grant Date -
Jul 24, 2014
app pub date -
Mar 21, 2014
filing date -
Feb 4, 2009
priority date (Note) -
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Abstract
Systems and methods are disclosed herein, such as those that operate to control a set of delays associated with one or more data clocks to clock a set of data bits into one or more transmit registers, one or more data strobes to transfer the set of data bits to at least one receive register, and/or a set of memory array timing signals to access a memory array on a die associated with a stacked-die memory vault. Systems and methods herein also include those that perform data eye training operations and/or memory array timing training operations associated with the stacked-die memory vault.
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