Memory array architecture with two-terminal memory cells
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United States of America Patent
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Apr 11, 2017
Grant Date -
Aug 13, 2015
app pub date -
Apr 21, 2015
filing date -
May 31, 2011
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Abstract
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
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