Integrated differential clock gater
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 18, 2017
Issued Date -
N/A
app pub date -
Mar 25, 2015
filing date -
Mar 25, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal. The apparatus includes a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully