High speed FPGA boot-up through concurrent multi-frame configuration scheme

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United States of America Patent

PATENT NO 9627019
APP PUB NO 20160307612A1
SERIAL NO

15197356

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Abstract

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Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

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Patent Owner(s)

  • ALTERA CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jong, Kiun Kiet Penang, MY 13 43
Tan, Jun Pin Selangor, MY 24 100
Tan, Lai Pheng Penang, MY 4 7

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