Solid electrolytic chip capacitor and manufacturing method thereof
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United States of America Patent
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Apr 18, 2017
Issued Date -
N/A
app pub date -
Oct 19, 2015
filing date -
Oct 28, 2014
priority date (Note) -
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Abstract
A solid electrolytic chip capacitor is provided which comprises a substrate layer, an electrical insulating block, a conductive polymer layer, a patterned reinforcement layer, and an electrode layer. The electrical insulating block is formed on the substrate layer to define an anode region and a cathode region on the substrate layer. The conductive polymer layer is formed to cover the cathode region of the substrate layer. The patterned reinforcement layer is formed to cover the conductive polymer. The electrode layer is formed to cover the patterned reinforcement layer. Whereby, the mechanical strength of the chip solid electrolytic capacitor can be improved without loss of capacitance.
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