Salvaging hardware transactions with instructions
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United States of America Patent
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May 2, 2017
Grant Date -
Jan 7, 2016
app pub date -
Sep 18, 2015
filing date -
Feb 27, 2014
priority date (Note) -
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Abstract
A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a first salvage checkpoint instruction in a code region during transactional execution of the code region, and based on the executing the first salvage checkpoint instruction, the processor records transaction state information comprising an address of the first salvage checkpoint instruction within the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, determines that the transaction state information been recorded, and further based on the detecting, executes an about-to-fail handler. Based on executing the about-to-fail handler, the processor returns to the execution of the code region of the transaction at the address of the checkpoint instruction.
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