Testability/manufacturing method to adjust output skew timing

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United States of America Patent

PATENT NO 9640278
SERIAL NO

14964953

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second control signal. The trimming circuit is generally enabled to vary a value of the first control signal to minimize a phase difference between the output signal and an output clock signal.

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Patent Owner(s)

  • INTEGRATED DEVICE TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Xi, Xiaoming San Jose, US 12 112

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