Optimizing power in a memory device

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United States of America Patent

PATENT NO 9645631
SERIAL NO

15248364

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amirkhany, Amir Sunnyvale, US 102 1048
Aquil, Farrukh San Diego, US 19 54
Kaviani, Kambiz Palo Alto, US 37 412
Patil, Dinesh Sunnyvale, US 36 139
Ware, Frederick A Los Altos Hill, US 757 10947

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