Memory cell and corresponding device
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United States of America Patent
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May 9, 2017
Issued Date -
N/A
app pub date -
Apr 27, 2016
filing date -
Jul 10, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
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