Vertical FET symmetric and asymmetric source/drain formation

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United States of America Patent

PATENT NO 9647120
SERIAL NO

15297377

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Abstract

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A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bi, Zhenxing Niskayuna, US 186 873
Cheng, Kangguo Schenectady, US 3073 29791
Li, Juntao Cohoes, US 578 3153
Xu, Peng Guilderland, US 640 4352

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