Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes
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United States of America Patent
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May 16, 2017
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app pub date -
May 28, 2015
filing date -
Aug 11, 2014
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Abstract
A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
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