Semiconductor memory device using grounded dummy bit lines
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United States of America Patent
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May 16, 2017
Grant Date -
Aug 25, 2016
app pub date -
Apr 15, 2015
filing date -
Feb 19, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor memory device according to an embodiment comprises a memory cell array including first and second wiring line layers disposed sequentially above memory cells, the first wiring line layer including a first wiring line and a first dummy wiring line, and the second wiring line layer including a second wiring line and a second dummy wiring line, the second wiring line being disposed at the same position in the first direction as the first dummy wiring line, the second dummy wiring line being disposed at the same position in the first direction as the first wiring line, and during an access operation by a control circuit, the first and second wiring lines being electrically connected to at least one of the memory cells, and the first and second dummy wiring lines being fixed at a certain first potential.
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