Asymmetric band gap junctions in narrow band gap MOSFET
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United States of America Patent
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May 16, 2017
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app pub date -
Sep 14, 2016
filing date -
Sep 14, 2016
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Abstract
A method for forming a semiconductor device, including forming one or more fin structures on a semiconductor substrate, where the fin structure defines source and drain regions. The method includes forming a gate stack, depositing a first contact insulator layer, and applying an etching process to portions of the first insulator layer to form a trench that extends to the source region. The method also includes depositing an epitaxial lower band gap source material into the trench and extending to the source region, depositing a second insulator layer, applying a second etching process to portions of the second insulator layer to form a trench that extends to the source and drain regions, and depositing a metalizing material over the substrate.
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